ARM cp15 c1,c0, 0 - control register configuration

ARM 的coprocessor cp15 ，可以用

mrc/mcr  p15,0,,Cn,Cm,N

來溝通 (read/write)
參考： cp15 instruction

比較常用的：Control Register Configuration:

MRC p15, 0, , c1, c0, 0  Read Control Register configuration data
MCR p15, 0, , c1, c0, 0 Write Control Register configuration data 

Control Register 內容參考：c1, Control Register
-- copy 過來，免得以後改位置--

Table 3.24. Control Register bit functions

Bits	Field	Function
[31]	SBZ	This field returns a Unpredictable value when read. Should Be Zero.
[30]	TE	Determines the state that the processor enters exceptions: 0 = Exceptions entered in ARM state 1 = Exceptions entered in Thumb state.
[29]	SBZ	Should Be Zero. This bit reads as 0 and ignores writes.
[28]	SBZ	Should Be Zero. This bit reads as 0 and ignores writes.
[27]	NMI	Determines the state of the non-maskable bit that is set by a configuration pin FIQISNMI: 0 = The processor is backwards compatible and behaves as normal 1 = All attempts to modify the CPSR F bit can only clear it. There is no way to set it in software. The SPSRs remain freely modifiable but copying the SPSR to CPSR can only clear the F bit. FIQs continue to set the F bit automatically. Note The status of the FIQISNMI pin is read by Bit 27. Software cannot write to Bit 27.
[26]	SBZ	Should Be Zero. This bit reads as 0 and ignores writes.
[25]	EE	Determines how the E bit in the CPSR bit is set on an exception: 0 = CPSR E bit is set to 0 on an exception 1 = CPSR E bit is set to 1 on an exception. The reset value depends on external signals, see Table 3.25.
[24]	VE	Enables the VIC interface to determine interrupt vectors: 0 = Interrupt vectors are fixed 1 = Interrupt vectors are defined by the VIC interface. See the description of the V bit, bit 13.
[23]	SBZ	Should Be Zero. This bit reads as 0 and ignores writes.
[22]	U	Enables unaligned data access operations for mixed little-endian and big-endian operation: 0 = Unaligned data access support disabled 1 = Unaligned data access support enabled. The A bit has priority over the U bit. The reset value of the U bit depends on external signals, see Table 3.25.
[21]	FI	Configures low latency features for fast interrupts. 0 = All performance features enabled. 1 = Low interrupt latency configuration enabled.
[20]	SBZ	Should Be Zero. This bit reads as 0 and ignores writes.
[19]	SBZ	Should Be Zero. This bit reads as 0 and ignores writes.
[18]	SBO	Should Be One. This bit reads as 1 and ignore writes.
[17]	SBZ	Should Be Zero. This bit reads as 0 and ignores writes.
[16]	SBO	Should Be One. This bit reads as 1 and ignore writes.
[15]	L4	Determines if the T bit is set for PC load instructions: 0 = Loads to PC set the T bit. 1 = Loads to PC do not set the T bit, ARMv4 behavior. For more details, see the ARM Architecture Reference Manual.
[14]	RR	Determines the replacement strategy for the cache: 0 = Normal replacement strategy by random replacement 1 = Predictable replacement strategy by round-robin replacement.
[13]	V	Determines the location of exception vectors: 0 = Normal exception vectors selected, address range = 0x00000000-0x0000001C 1 = High exception vectors selected, address range = 0xFFFF0000-0xFFFF001C.
[12]	I	Enable or disable level one instruction cache: 0 = disabled 1 = enabled.
[11]	Z	Enables programme flow prediction: 0 = Program flow prediction disabled 1 = Program flow prediction enabled.
[10:8]	SBZ	Should Be Zero. This bit reads as 0 and ignores writes.
[7]	B	Determines operation as little-endian or big-endian memory system and the names of the low four-byte addresses within a 32-bit word: 0 = Little-endian memory system 1 = Big-endian word-invariant memory system. The reset value of the B bit depends on external signals, see Table 3.25.
[6:3]	SBO	Should Be One. This field read as 1 and ignore writes.
[2]	C	Enables or disables level one data cache: 0 = Data cache disabled 1 = Data cache enabled.
[1]	A	Enables strict alignment of data to detect alignment faults in data accesses: 0 = Strict alignment fault checking disabled. 1 = Strict alignment fault checking enabled. The A bit setting takes priority over the U bit.
[0]	M	Enables or disables the MPU: 0 = MPU disabled 1 = MPU enabled.