for ibus

  export GTK_IM_MODULE=ibus
  export XMODIFIERS=@im=ibus
  export QT_IM_MODULE=ibus

SD card cannot be identified,

SD card 有一些不能 idenfy。
進入發現是 identification error.

trace initialize procedure:

* CMD0
* CMD8
* ACMD41 - repeat,
* Ready

在 ACMD41 時，一直response not ready。
因為是有 response，不是 timeout，所以 hardware trace layout 應該是OK的。

只有猜是因為 ACMD41 command 後，card要作 voltage switch，猜測是 power 的問題，所以請 hardware 在 SDcard socket 端 power 加上電容，就 OK了。


這個有關 SD card inititlize 的 討論：
http://www.avrfreaks.net/index.php?name=PNphpBB2&file=viewtopic&p=620292

這一篇說得很清楚，附圖，和 SD spec, 和 procedure
http://blog.chinaunix.net/u1/58780/showart.php?id=673609

這一篇講 ACMD41的動作
http://hi.baidu.com/lizhenqian79/blog/item/620420a10bc7ce88471064bb.html

這一篇也有說ACMD41:
http://www.laogu.com/laogubbs/see_30547.htm

acmd41的返回值中,OCR的bit31为0表明卡此时处于busy状态,*请隔50ms后重新发cmd55,acmd41命令*,重复**部分直到返回的OCR的bit31为1为止.请仔细阅读spec.

這一篇有 SD card spec 的 link
http://hi.baidu.com/hao01222/blog/item/f69a48554c53dec7b745ae9e.html

EBOOT 的 pTOC 變數是由 ROMIMAGE.EXE 賦予初值

KernelRelocate(ROMHDR *const pToc);

Eboot 啟動後，先作這個，但是查code，pToc 只有宣告，並沒有賦予初值。
在 這篇：CE5.0 - romimage.exe如何填充eboot.bin中的pTOC特殊指針生成.nb0 有說明。

原來是 romimage.exe 做的，romimage 為EBOOT.bin 建立 pTOC (ROMHDR)，然後在找到 EBOOT.bin 中 的 pTOC token，修改他的初值，改為romimage 建立的 pTOC (ROMHDR)。

所以說，pTOC 的初值是 ROMIMAGE.EXE 給的。

根據參考的那一篇，說明這個 romiage--pTOC--KernelRelocate( ) 的配合動作是為了達成類似 C startup function 對各變數region 的初始設定。可以看 KernelRelocate( ) 的 source code 就可以了解，跟 C Startup Code 類似。

memory relocate file : scat_romboot
分成三個區域：
* 0x70000000 : startup
* 0x8C008000 :wakeup
* 0x00000000 : vectors


0x70000000 是 chip 內建的SRAM 區域。
外接的DDR/SDRAM位址區域是 0xC0000000

startup :

cp15 control : disable mmu. enable i-cache.
SDRAM/DDR

NBOOT 使用 0x00100000:

|-------------------------
| SVC STACK
-------------------------
|0x0400 : L2 cache
--------------------------
|0x4000 :  pagetable
--------------------------

原來ARM11有這麼多版本，這個用的是 ARM1136JF-S。
所以有MMU，CP15也有MMU操作指令。

ARM 文件上描述 cp15 operation 的指令是：

mcr/mrc  p15, op1, , Rn, Rm, op2

在說明文件中常常用 Rn,op1, Rm, op2 來列表。

基本上好像是利用 Rn 作 block selection， Rm 作 function selectio, op2 才是 register selection

我猜的 :p

ARM cp15 c1,c0, 0 - control register configuration

ARM 的coprocessor cp15 ，可以用

mrc/mcr  p15,0,,Cn,Cm,N

來溝通 (read/write)
參考： cp15 instruction

比較常用的：Control Register Configuration:

MRC p15, 0, , c1, c0, 0  Read Control Register configuration data
MCR p15, 0, , c1, c0, 0 Write Control Register configuration data 

Control Register 內容參考：c1, Control Register
-- copy 過來，免得以後改位置--

Table 3.24. Control Register bit functions

Bits	Field	Function
[31]	SBZ	This field returns a Unpredictable value when read. Should Be Zero.
[30]	TE	Determines the state that the processor enters exceptions: 0 = Exceptions entered in ARM state 1 = Exceptions entered in Thumb state.
[29]	SBZ	Should Be Zero. This bit reads as 0 and ignores writes.
[28]	SBZ	Should Be Zero. This bit reads as 0 and ignores writes.
[27]	NMI	Determines the state of the non-maskable bit that is set by a configuration pin FIQISNMI: 0 = The processor is backwards compatible and behaves as normal 1 = All attempts to modify the CPSR F bit can only clear it. There is no way to set it in software. The SPSRs remain freely modifiable but copying the SPSR to CPSR can only clear the F bit. FIQs continue to set the F bit automatically. Note The status of the FIQISNMI pin is read by Bit 27. Software cannot write to Bit 27.
[26]	SBZ	Should Be Zero. This bit reads as 0 and ignores writes.
[25]	EE	Determines how the E bit in the CPSR bit is set on an exception: 0 = CPSR E bit is set to 0 on an exception 1 = CPSR E bit is set to 1 on an exception. The reset value depends on external signals, see Table 3.25.
[24]	VE	Enables the VIC interface to determine interrupt vectors: 0 = Interrupt vectors are fixed 1 = Interrupt vectors are defined by the VIC interface. See the description of the V bit, bit 13.
[23]	SBZ	Should Be Zero. This bit reads as 0 and ignores writes.
[22]	U	Enables unaligned data access operations for mixed little-endian and big-endian operation: 0 = Unaligned data access support disabled 1 = Unaligned data access support enabled. The A bit has priority over the U bit. The reset value of the U bit depends on external signals, see Table 3.25.
[21]	FI	Configures low latency features for fast interrupts. 0 = All performance features enabled. 1 = Low interrupt latency configuration enabled.
[20]	SBZ	Should Be Zero. This bit reads as 0 and ignores writes.
[19]	SBZ	Should Be Zero. This bit reads as 0 and ignores writes.
[18]	SBO	Should Be One. This bit reads as 1 and ignore writes.
[17]	SBZ	Should Be Zero. This bit reads as 0 and ignores writes.
[16]	SBO	Should Be One. This bit reads as 1 and ignore writes.
[15]	L4	Determines if the T bit is set for PC load instructions: 0 = Loads to PC set the T bit. 1 = Loads to PC do not set the T bit, ARMv4 behavior. For more details, see the ARM Architecture Reference Manual.
[14]	RR	Determines the replacement strategy for the cache: 0 = Normal replacement strategy by random replacement 1 = Predictable replacement strategy by round-robin replacement.
[13]	V	Determines the location of exception vectors: 0 = Normal exception vectors selected, address range = 0x00000000-0x0000001C 1 = High exception vectors selected, address range = 0xFFFF0000-0xFFFF001C.
[12]	I	Enable or disable level one instruction cache: 0 = disabled 1 = enabled.
[11]	Z	Enables programme flow prediction: 0 = Program flow prediction disabled 1 = Program flow prediction enabled.
[10:8]	SBZ	Should Be Zero. This bit reads as 0 and ignores writes.
[7]	B	Determines operation as little-endian or big-endian memory system and the names of the low four-byte addresses within a 32-bit word: 0 = Little-endian memory system 1 = Big-endian word-invariant memory system. The reset value of the B bit depends on external signals, see Table 3.25.
[6:3]	SBO	Should Be One. This field read as 1 and ignore writes.
[2]	C	Enables or disables level one data cache: 0 = Data cache disabled 1 = Data cache enabled.
[1]	A	Enables strict alignment of data to detect alignment faults in data accesses: 0 = Strict alignment fault checking disabled. 1 = Strict alignment fault checking enabled. The A bit setting takes priority over the U bit.
[0]	M	Enables or disables the MPU: 0 = MPU disabled 1 = MPU enabled.

DRAM 起始位址0x8C000000，none-cached address (就是+20000000)是 0xAC000000 。

然後預留 0x2000 給.. interrupt handler ?

接著就是整個 kernel 都可以 access 的 global variable。
利用直接address 定址，大家都可以讀，大家都可以改，所以就是一團混亂！！

管理的方法就是宣告一個 structure，用 structure 來 access 這一塊區域的資料。

CleanOS

下 CleasOS 時，執行的動作:

Starting Build: cleanos.bat
==============
CLEAN.BAT: Cleaning Sysgen directory "C:\WINCE600\OSDesigns\OSDesign1\OSDesign1\Wince600\TT4X0BD_ARMV4I\cesysgen"
CLEAN.BAT: Cleaning platform directory C:\WINCE600\platform\MyBoard\target\ARMV4I\retail
CLEAN.BAT: Cleaning platform directory C:\WINCE600\platform\MyBoard\lib\ARMV4I\retail
CLEAN.BAT: Cleaning platform common directory C:\WINCE600\platform\common\target\ARMV4I\retail
CLEAN.BAT: Cleaning platform common directory C:\WINCE600\platform\common\lib\ARMV4I\retail
CLEAN.BAT: Cleaning flat release directory "C:\WINCE600\OSDesigns\OSDesign1\OSDesign1\RelDir\MyBoard_ARMV4I_Release"

missing aygshell.h in CE 6.0 SDK

故事參考這一篇

或是google aygshell.h mfc

使用 VS2005 的 mfc for smart device 竟然會 incluse aygshell.h , shellsdk.h
aygshell.h 要加入 aygshell 這個 component 才能用。但是 aygshell 不屬於 core license (也就是說，加了是要加錢的)。

原來在 CE 5.0 build mfc code 時不會 complain，因為 CE 5.0 的SDK 在產生時，不管你有沒有加 aygshell，都會把 aygshell.h 放進去。

但是到 CE 6.0 後，就不這樣作了。

所以？有人 report 給 MS 了。

在 MS patch 之前 (會有patch嗎？)

只好自己加入 這兩個 header 檔 -- 這樣要加錢嗎？

---

aygshell.h 在

C:\WINCE600\PUBLIC\SHELLSDK\SDK\INC

shellsdk.h 在

C:\WINCE600\PUBLIC\COMMON\SDK\INC

感想：也只有作MS的programmer 才要考慮這種問題。不要錢的 include 要錢的 component.....唉！

source code location : CE 6.0 control panel applet

CE control panel 裡的 applet 的 source 在

C:\WINCE600\PUBLIC\WCESHELLFE\OAK\CTLPNL\CPLMAIN

切換 usb profile

依照慣例，我又在copy人家的code..:p

這一篇

USB Function profile switcher

示範了application 變更 usb profile 的code:

先說OS 內建支援的 profile 都列在： [HKEY_LOCAL_MACHINE\Drivers\USB\FunctionDrivers]

下面的code sample 就是作者(Nicloas BESSON)提供的，切換activesync 和 mass storage 的 code:

void SwitchUSBFunctionProfile(BOOL bEnableActiveSync)
{
HANDLE hUSBFn;
UFN_CLIENT_INFO info;
DWORD dwBytes;

// Open the USB function driver
hUSBFn = CreateFile(USB_FUN_DEV, DEVACCESS_BUSNAMESPACE,
       0, NULL, OPEN_EXISTING, FILE_ATTRIBUTE_NORMAL,
       NULL);

if(bEnableActiveSync)
{
// Enable USB Function profile for activesync
swprintf(info.szName, _T("Serial_Class"));
DeviceIoControl(hUSBFn, IOCTL_UFN_CHANGE_CURRENT_CLIENT,
 info.szName, sizeof(info.szName), NULL, 0, &dwBytes, NULL))
}
else
{
// Enable USB Function for mass-storage
swprintf(info.szName, _T("Mass_Storage_Class"));
DeviceIoControl(hUSBFn, IOCTL_UFN_CHANGE_CURRENT_CLIENT,
 info.szName, sizeof(info.szName), NULL, 0, &dwBytes, NULL);
}
}

我完整而沒有修改的 copy 過來。

上述使用到的 define value 都在

The defines values are located in %_WINCEROOT%\PUBLIC\COMMON\OAK\INC\usbfnioctl.h

方法大概是用 USB_FUN_DEV 提供的 IOControl -

IOCTL_UFN_CHANGE_CURRENT_CLIENT

來變換，吃的 argument 是 描述 profile 的字串。